1. Technical Field
The present invention relates to a semiconductor device. More specifically, the invention relates to a technology that realizes electrical erasure in a FAMOS without increasing the number of processes.
2. Related Art
Among related art semiconductor memory devices is one called a FAMOS that realizes a non-volatile memory element if only it is provided with one MIS transistor having a floating gate structure. In the FAMOS, writing is performed by injection of hot electrons into the floating gate, the hot electrons having been generated through the avalanche breakdown of a PN junction formed between an N-type semiconductor substrate and a P-type drain layer. Also, reading is performed in the FAMOS through use of a shift in the threshold voltage, the shift occurring at the time when electrons are injected into the floating gate.
JP-A-10-178115 and JP-A-5-55602 are examples of related art. JP-A-10-178115, for example, discloses a method of realizing an electrically erasable FAMOS by depositing a control gate on the floating gate with an insulating film therebetween and electrically erasing carriers, having been accumulated at the floating gate, through tunneling.
However, in a related art FAMOS, once electrons have been injected into a floating gate, it is difficult to extract the electrons from the floating gate by means of an electrical technique. Thus, undesirably, information written into a FAMOS cannot be erased, which precludes repetition of the writing procedure. Furthermore, the method disclosed in JP-A-10-178115 requires that a control gate is deposited on the floating gate, with an insulating film therebetween, in order for an erasing action to be electrically realized in a FAMOS. This incurs a disadvantage that the number of processes is increased.